Renesas H8 Series - Page 289

Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 247 of 652
REJ09B0042-0700
Block Diagram
Figure 9.1 shows a block diagram of timer A.
φ
W
PSW
Internal data bus
PSS
[Legend]
1/4
TMA
TCA
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
IRRT
A
+8
*
+64
*
+128
*
+256
*
φ
W
/4
φ
W
/128
TMA:
TCA:
IRRTA:
PSW:
PSS:
Note:
* Can be selected only when the prescaler W output (φ
W
/128) is used as the TCA input clock.
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
φ
Figure 9.1 Block Diagram of Timer A