Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 259 of 652
REJ09B0042-0700
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: For details on interrupts, see section 3.3, Interrupts.
Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
Event Counter Operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C (TMC) to all 1s (111). TCC counts up/down at the rising/falling edge of an
external event signal input at pin TMIC.
When timer C is used to count external event input, bit IRQ1 in PMRB should be set to 1 and bit
IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests.
TCC Up/Down Control by Hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC
is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter
when high.
When using UD pin input, set bit UD in PMR3 to 1.
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