Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 305 of 652
REJ09B0042-0700
Bit 2
WDON Description
0 Watchdog timer operation is disabled (initial value)
*
Clearing conditions:
Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that
a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but
sets WDON to 1 on the H8/38124 Group.
Note: * Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial
value is 1 on H8/38124 Group.
1 Watchdog timer operation is enabled
Setting condition:
When TCSRWE is set to 1 and 0 is written to B2WI and 1 is written to WDON
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI Description
0 Bit 0 is write-enabled
1 Bit 0 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 0—Watchdog Timer Reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES
pin, or when software writes 0.
Bit 0
WRST Description
0
Clearing conditions:
Reset by
RES
pin
When TCSRWE = 1, and 0 is written in both BOWI and WRST
1
Setting condition:
When TCW overflows and an internal reset signal is generated
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