Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 321 of 652
REJ09B0042-0700
Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL Description
0 ECL event clock input is disabled (initial value)
ECL value is held
1 ECL event clock input is enabled
Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH Description
0 ECH is reset (initial value)
1 ECH reset is cleared and count-up function is enabled
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL Description
0 ECL is reset (initial value)
1 ECL reset is cleared and count-up function is enabled
Event Counter H (ECH)
ECH7 ECH2 ECH1 ECH0ECH6 ECH5 ECH4 ECH3
76543210
0
0000000
R
RRR
RRR
R
Bit
Initial Value
Read/Write
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