Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 329 of 652
REJ09B0042-0700
Mode
Maximum AEVH/AEVL Pin Input
Clock Frequency
Active (high-speed), sleep (high-speed) 16 MHz
Active (medium-speed), sleep (medium-speed) (φ/16)
(φ/32)
(φ/64)
f
OSC
= 1 MHz to 4 MHz (φ/128)
2 • f
OSC
f
OSC
1/2 • f
OSC
1/4 • f
OSC
Watch, subactive, subsleep, standby (φw/2)
(φw/4)
φw = 32.768 kHz or 38.4 kHz
*
(φw/8)
1000 kHz
500 kHz
250 kHz
Note: * Does not apply to H8/38124 Group.
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 t
cyc
will occur between clock halting and interrupt acceptance.
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