Renesas H8 Series Hardware Manual

Section 10 Serial Communication Interface
Rev. 7.00 Mar 10, 2005 page 350 of 652
REJ09B0042-0700
Table 10.4 Relation between n and Clock
SMR Setting
n Clock CKS1 CKS0
0 φ 00
0 φw/2
*
1
/φw
*
2
01
2 φ/16 1 0
3 φ/64 1 1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz) φ
φφ
φ (MHz)
Maximum Bit Rate
(bit/s)
nN
0.0384
*
0.0192 600 0 0
2 1 31250 0 0
2.4576 1.2288 38400 0 0
4 2 62500 0 0
10 5 156250 0 0
16 8 250000 0 0
20 10 312500 0 0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English