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Section 10 Serial Communication Interface

Rev. 7.00 Mar 10, 2005 page 381 of 652

REJ09B0042-0700

Start receive

error processing

End of receive

error processing

Clear bits OER and

FER to 0 in SSR

Yes

OER = 1?

Yes

FER = 1?

Break?

Overrun error

processing

Framing error

processing

(A)

Figure 10.19 Example of Multiprocessor Data Reception Flowchart (cont)

Figure 10.20 shows an example of the operation when receiving using the multiprocessor format.

Default Chapter31
- Table of Contents31
Section 1 Overview43
- Overview43
- Internal Block Diagram49
- Pin Arrangement and Functions51
  - Pin Arrangement51
  - Pin Functions61
Section 2 CPU67
- Overview67
- Register Descriptions69
- Data Formats71
  - Data Formats in General Registers72
  - Memory Data Formats73
- Addressing Modes74
  - Effective Address Calculation76
- Instruction Set80
- Basic Operational Timing97
  - Access to On-Chip Memory (RAM, ROM)97
  - Access to On-Chip Peripheral Modules98
- CPU States99
- Memory Map102
- Application Notes108
Section 3 Exception Handling117
- Overview117
- Reset117
  - Reset Sequence117
  - Interrupt Immediately after Reset118
- Interrupts119
- Application Notes140
Section 4 Clock Pulse Generators145
- Overview145
- System Clock Generator148
- Subclock Generator153
- Prescalers155
- Note on Oscillators156
- Notes on H8/38124 Group160
Section 5 Power-Down Modes161
- Overview161
  - System Control Registers164
- Sleep Mode168
- Standby Mode170
- Watch Mode174
- Subsleep Mode176
  - Transition to Subsleep Mode176
  - Clearing Subsleep Mode176
- Subactive Mode177
- Active (Medium-Speed) Mode178
- Direct Transfer179
- Module Standby Mode183
  - Setting Module Standby Mode183
  - Clearing Module Standby Mode183
Section 6 ROM185
- Overview185
  - Block Diagram185
- H8/38024 PROM Mode186
  - Setting to PROM Mode186
  - Socket Adapter Pin Arrangement and Memory Map186
- H8/38024 Programming189
  - Writing and Verifying189
  - Programming Precautions194
- Reliability of Programmed Data195
- Flash Memory Overview196
- Descriptions of Registers of the Flash Memory200
- On-Board Programming Modes206
- Flash Memory Programming/Erasing210
- Program/Erase Protection216
- Programmer Mode217
- Power-Down States for Flash Memory231
Section 7 RAM233
- Overview233
  - Block Diagram233
Section 8 I/O Ports235
- Overview235
- Port 1237
- Port 3244
- Port 4251
- Port 5255
- Port 6260
- Port 7264
- Port 8267
- Port 9270
- Port a275
- Port B279
- Input/Output Data Inversion Function282
- Application Note285
  - The Management of the Un-Use Terminal285
Section 9 Timers287
- Overview287
- Timer a288
- Timer C295
- Timer F303
- Timer G323
- Watchdog Timer342
- Asynchronous Event Counter (AEC)353
Section 10 Serial Communication Interface373
- Overview373
- Register Descriptions377
- Operation398
- Interrupts425
- Application Notes426
Section 11 10-Bit PWM431
- Overview431
- Register Descriptions434
- Operation438
  - PWM Operation Modes439
Section 12 A/D Converter441
- Overview441
- Register Descriptions444
- Operation448
- Interrupts449
- Typical Use449
- A/D Conversion Accuracy Definitions453
- Application Notes455
Section 13 LCD Controller/Driver457
- Overview457
- Register Descriptions461
- Operation468
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)477
- Overview477
- Individual Register Descriptions479
- Operation485
  - Power-On Reset Circuit485
  - Low-Voltage Detection Circuit486
Section 15 Power Supply Circuit (H8/38124 Group Only)493
- When Using Internal Power Supply Step-Down Circuit493
- When Not Using Internal Power Supply Step-Down Circuit494
Section 16 Electrical Characteristics495
- H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum Ratings495
- H8/38024 Group ZTAT Version and Mask ROM Version Electrical Characteristics496
- H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute Maximum Ratings511
- H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical Characteristics512
- H8/38024S Group Mask ROM Version Absolute Maximum Ratings529
- H8/38024S Group Mask ROM Version Electrical Characteristics530
- Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM Version547
- Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM Version548
- Operation Timing571
- Output Load Circuit574
- Resonator Equivalent Circuit574
- Usage Note575
Appendix A CPU Instruction Set577
- Instructions577
- Operation Code Map585
- Number of Execution States587
Appendix B Internal I/O Registers592
- Addresses592
- Functions597
- B.2 Functions597
Appendix C I/O Port Block Diagrams658
- Block Diagrams of Port 1658
- Block Diagrams of Port 3661
- Block Diagrams of Port 4666
- Block Diagram of Port 5670
- Block Diagram of Port 6671
- Block Diagram of Port 7672
- Block Diagram of Port 8673
- Block Diagrams of Port 9674
- Block Diagram of Port a676
- Block Diagrams of Port B677
Appendix D Port States in the Different Processing States680
Appendix E List of Product Codes681
Appendix F Package Dimensions685
Appendix G Specifications of Chip Form689

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English

Renesas H8 Series Hardware Manual

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