Section 12 A/D Converter
Rev. 7.00 Mar 10, 2005 page 403 of 652
REJ09B0042-0700
Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7
CKS Conversion Period φ
φφ
φ = 1 MHz φ
φφ
φ = 5 MHz φ
φφ
φ = 10 MHz
*
2
0 62/φ (initial value) 62 µs 12.4 µs 6.2 µs
1 31/φ 31 µs —
*
1
—
*
1
Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed
if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a
conversion time of 12.4 µs or more.
With the H8/38124 Group operation cannot be guaranteed if the conversion time is less
than 6.2 µs. Make sure to select a setting that gives a conversion time of 6.2 µs or
more.
2. H8/38124 Group only.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE Description
0 Disables start of A/D conversion by external trigger (initial value)
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG
*
Note: * The external trigger (
ADTRG
) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2 for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
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