Section 13 LCD Controller/Driver
Rev. 7.00 Mar 10, 2005 page 422 of 652
REJ09B0042-0700
Bit 4—Display Data Control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP Description
0 Blank data is displayed (initial value)
1 LCD RAM data is display
Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
Frame Frequency
*
2
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0 Operating Clock φ
φφ
φ = 2 MHz φ
φφ
φ = 250 kHz
*
1
0 * 00φw 128 Hz
*
3
(initial value)
0 * 01φw/2 64 Hz
*
3
0 * 1 * φw/4 32 Hz
*
3
1000φ/2 — 244 Hz
1001φ/4 977 Hz 122 Hz
1010φ/8 488 Hz 61 Hz
1011φ/16 244 Hz 30.5 Hz
1100φ/32 122 Hz —
1101φ/64 61 Hz —
1110φ/128 30.5 Hz —
1111φ/256 — —
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
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