Renesas H8 Series Hardware Manual

Appendix A CPU Instruction Set
Rev. 7.00 Mar 10, 2005 page 546 of 652
REJ09B0042-0700
Table A.4 Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
O
p
eration
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation N
ADD ADD.B #xx:8, Rd 1
ADD.B Rs, Rd 1
ADD.W Rs, Rd 1
ADDS ADDS.W #1, Rd 1
ADDS.W #2, Rd 1
ADDX ADDX.B #xx:8, Rd 1
ADDX.B Rs, Rd 1
AND AND.B #xx:8, Rd 1
AND.B Rs, Rd 1
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd 1
BAND #xx:3, @Rd 2 1
BAND #xx:3, @aa:8 2 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
BCLR BCLR #xx:3, Rd 1
BCLR #xx:3, @Rd 2 2
BCLR #xx:3, @aa:8 2 2
BCLR Rn, Rd 1
BCLR Rn, @Rd 2 2
BCLR Rn, @aa:8 2 2
BIAND BIAND #xx:3, Rd 1
BIAND #xx:3, @Rd 2 1
BIAND #xx:3, @aa:8 2 1

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English