Renesas H8 Series - Page 617

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 575 of 652
REJ09B0042-0700
TCSRW—Timer Control/Status Register W H'B2 Watchdog Timer
Bit
Initial value
Read/Write
7
B6WI
1
R
6
TCWE
0
R/(W)
*
1
5
B4WI
1
R
3
B2WI
1
R
0
WRST
0
R/(W)
*
1
2
WDON
0
*
2
R/(W)
*
1
1
BOWI
1
R
4
TCSRWE
0
R/(W)
*
1
Watchdog Timer Reset
0 Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written
in both B0WI and WRST
1 Setting condition:
When TCW overflows and an internal
reset signal is generated
Watchdog Timer On
0 Watchdog timer operation is disabled
Clearing conditions:
Reset
*
2
, or 0 is written in both B2WI and WDON
while TCSRWE = 1
1 Watchdog timer operation is enabled
Setting condition:
0 is written in B2WI and 1 is written in WDON
while TCSRWE = 1
Bit 0 Write Inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-disabled
Bit 2 Write Inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-disabled
Timer Control/Status Register W Write Enable
0 Data cannot be written to bits 2 and 0
1 Data can be written to bits 2 and 0
Bit 4 Write Inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-disabled
Timer Counter W Write Enable
0 8-bit data cannot be written to TCW
1 8-bit data can be written to TCW
Bit 6 Write Inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-disabled
Notes: 1. Write is permitted only under certain conditions.
2. 1 on the H8/38124 Group.