DCO Setup and Calibration
The UCS API found in the MSP430ware DriverLib makes setting up the FLL and DCO easy.
As seen below, you must first configure the FLL reference clock using the UCS_clockSignalInit()
function. (In this example, we used REFO as the FLL reference clock.)
Setting ‘F5529 DCO with MSP430ware
UCSCTL0 DCO MOD
UCSCTL1 DCORSEL
UCSCTL2 FLLD FLLN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
#include <driverlib.h>
#define MCLK_FREQ_KHZ 8000
#define FLLREF_KHZ 32
#define MCLK_FLLREF_RATIO MCLK_FREQ_KHZ/FLLREF_KHZ // Ratio=250
void myInitDCO (void) {
// Set DCO FLLREF to 32KHz = REF0
UCS_clockSignalInit ( UCS_BASE,
UCS_FLLREF, // Setup FLLREFCLK
UCS_REFOCLK_SELECT, // FLLREFCLK=REFO
UCS_CLOCK_DIVIDER_1 // FLLREFDIV=1
);
// Setup DCO and FLL to provided freq (sets FLLD, FLLN, etc.)
// once clk settled, use as source for MCLK & SMCLK
UCS_initFLLSettle( UCS_BASE,
MCLK_FREQ_KHZ,
MCLK_FLLREF_RATIO);
}
With the FLL reference clock set, the UCS_initFLLSettle() function configures the FLL and DCO
using the two clock frequencies you’ve chosen (DCOCLK and FLLREFCLK). Additionally, this
function adds time needed for the FLL feedback loop to ‘settle’. Alternatively, you could use the
UCS_initFLL() function if you didn’t want the function to add the clock settling time.
Note: The UCS initFLL functions configure both MCLK and SMCLK. A common mistake is to
configure SMCLK before calling the FLL init function.
For example, when creating our optional lab exercise, we configured SMCLK to use the
XT2 high-frequency crystal before configuring the FLL. We didn’t find our mistake until we
realized that SMCLK was running at the same speed as MCLK.
One last note, the initFLL functions will set MCLK and SMCLK to DCOCLK if the frequency is
greater than 16MHz, otherwise it will use the divided down DCOCLKDIV.
4 - 30 MSP430 Workshop - MSP430 Clocks & Initialization
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