Xinje XD Series - Page 128

127
64 bits
QDEC
Execution
condition
Normal ON/OFF/falling or
rising pulse edge
Suitable
Models
XDH, XLH
Hardware
requirement
Version V3.7.1 or later
Software
requirement
Version V3.7.4a or later
2) Operands
Operands
Function
Data Type
D
The increase or decrease data address
16 bits / 32 bits/64 bits,BIN
3) Suitable soft components
Operan
ds
Word soft elements
Bit soft elements
System
Consta
nt
Modul
e
System
D
F
D
T
D
C
D
D
X
D
Y
D
M
D
S
K/H
I
D
Q
D
X
Y
M
S
T
C
Dn.
m
D
●
●
●
●
●
●
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD; DM
includes DM, DHM; DS includes DS, DHS. M includes M,HM,SM；S includes S,HS；T
includes T,HT；C includes C, HC.
< Increment [INC]>
INC D0
X0
D·
 D will increase one when X0 is ON.
 For 16 bits operation, when +32767 increase one, it will become -32768; The flag bit will act.
for 32 bits operation, +2147483647 increases one is -2147483647. The flag bit will act.
for 64 bits operation, +9223372036854775807 increases one is -9223372036854775808. The
flag bit will act.
<Decrement [DEC]>
DEC D0
X1
D·
 D will decrease one when X1 is ON.
 -32767 or -2147483647 decrease one, the result will be +32767 or +2147483647. The flag bit
will act. For 64 bits operation, -9223372036854775808 decrease one is
+9223372036854775807. The flag bit will act.
 The addresses of operands in QINC and QDEC instruction must be even.
Description
(D0) ＋1→(D0)
(D0) －1 → (D0)
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