Tightly-Coupled Memory Interface
5-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Figure 5-10 DMA with single wait state for nonsequential accesses
The logic used to generate DRWAIT uses both the loopback scheme using DRSEQ for
inserting a wait state for a nonsequential request, and an additional signal DMAWAIT,
for stalling during DMA accesses. The FORCE_NSEQ signal is an override signal
used to force the ARM926EJ-S access to be treated as nonsequential because of an
intervening DMA access.
The A, WE and nRW inputs to the TCM are either sourced directly from the
ARM926EJ-S TCM interface, from the DMA controller, or from the capture register
(clocked by REQCLK) if the ARM926EJ-S access is postponed because of DMA
activity.
The cycle timing of the circuit shown in Figure 5-10 is shown in Figure 5-11 on
page 5-17.
TCM
DRRD[31:0]
DRADDR[17:0]
DRCS
DRSEQ
DRWAIT
DRWD[31:0]
DRWBL[3:0]
DRnRW
SEQ
CS
A, WE,
nRW
WD RD
REQCLK
DMA WD
FORCE_NSEQ
DMAWAIT
DMA (A,
WE, nRW)
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