Signal Descriptions
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-9
A.5 JTAG signals
Table A-4 describes the ARM926EJ-S processor JTAG signals.
Table A-4 JTAG signals
Name Direction Description
DBGIR[3:0]
TAP controller
instruction register
Output These four bits reflect the current instruction loaded
into the TAP controller instruction register. These bits
change when the TAP controller is in the
UPDATE-IR state.
DBGnTRST
Not test reset
Input This is the active LOW reset signal for the
EmbeddedICE-RT internal state. This signal is a
level-sensitive asynchronous reset input.
DBGnTDOEN
Not DBGTDO enable
Output When LOW, indicates that the serial data is being
driven out of the DBGTDO output. Normally used as
an output enable for a DBGTDO pin in a packaged
part.
DBGSCREG[4:0] Output These five bits reflect the ID number of the scan chain
currently selected by the TAP controller. These bits
change when the TAP controller is in the
UPDATE-DR state.
DBGSDIN
External scan chain
serial input data
Output Contains the serial data to be applied to an external
scan chain.
DBGSDOUT
External scan chain
serial data output
Input Contains the serial data out of an external scan chain.
When an external scan chain is not connected, this
signal must be tied LOW.
DBGTAPSM[3:0]
TAP controller state
machine
Output This bus reflects the current state of the TAP
controller state machine.
DBGTCKEN Input Synchronous test clock enable.
DBGTDI Input Test data input for debug logic.
DBGTDO Output Test data output from debug logic.
DBGTMS Input Test mode select for TAP controller.
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