CP15 Test and Debug Registers
B-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Table B-12 describes the bit fields of the Memory Region Remap Register.
Table B-13 shows the encoding of each of the remap fields.
Table B-12 Encoding of the Memory Region Remap Register
Bit Name Definition Reset state
[31:16] - Should Be Zero
0x0000
[15:14] IWB Remap select bits for instruction-side write-back region b11
[13:12] IWT Remap select bits for instruction-side write-through region b10
[11:10] INCB Remap select bits for instruction-side noncachable bufferable region b01
[9:8] INCNB Remap select bits for instruction-side noncachable nonbufferable region b00
[7:6] DWB Remap select bits for data-side write-back region b11
[5:4] DWT Remap select bits for data-side write-through region b10
[3:2] DNCB Remap select bits for data-side noncachable bufferable region b01
[1:0] DNCNB Remap select bits for data-side noncachable nonbufferable region b00
Table B-13 Encoding of the remap fields
Remap field
b00 = noncachable nonbufferable
b01 = noncachable bufferable
b10 = write-through
b11 = write-back
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