Programmer’s Model
2-24 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Figure 2-10 Register c7 Set/Way format
Test and clean operations
The test and clean DCache instruction provides an efficient way to clean the entire
DCache using a simple loop. The test and clean DCache instruction tests a number of
lines in the DCache to determine if any of them are dirty. If any dirty lines are found,
then one of those lines is cleaned. The test and clean DCache instruction also returns the
status of the entire DCache in bit 30.
Note
The test and clean DCache instruction,
MRC p15, 0, r15, c7, c10, 3
, is a special
encoding that uses r15 as a destination operand. However, the PC is not changed by
using this instruction. This MRC instruction also sets the condition code flags.
If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty lines,
bit 30 is set to 1. This means that you can use the following loop to clean the entire
DCache:
tc_loop: MRC p15, 0, r15, c7, c10, 3 ; test and clean
BNE tc_loop
The test, clean, and invalidate DCache instruction is the same as test and clean DCache,
except that when the entire cache has been cleaned, it is invalidated. This means that
you can use the following loop to clean and invalidate the entire DCache:
tci_loop: MRC p15, 0, r15, c7, c14, 3 ; test clean and invalidate
BNE tci_loop
2.3.9 TLB Operations Register c8
This is a write-only register used to control the Translation Lookaside Buffer (TLB).
There is a single TLB used to hold entries for both data and instructions. The TLB is
divided into two parts:
• a set-associative part
• a fully-associative part.
Way
31 32-A 31-A S+5 S+4 5 4 2 1 0
SBZ Set (= index) Word SBZ
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