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Tightly-Coupled Memory Interface

Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses

The address and chip-select inputs to the ROM are pipelined with respect to the

ARM926EJ-S TCM interface outputs. An address incrementer is used to generate

sequential addresses. The output of the incrementer is captured at the end of every cycle

where the ROM CS chip select is active. The address source for the ROM is switched

over to the registered version of IRADDR when a nonsequential access occurs.

Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read

data relative to the ARM926EJ-S TCM interface signals. The address supplied to the

ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type

of memory access and the presence of idle cycles.

ROM

IRRD[31:0]

IRADDR[17:0]

IRCS

IRSEQ

IRWAIT

ARM926EJ-S

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ARM ARM926EJ-S Specifications

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