ARM ARM926EJ-S User Manual

Caches and Write Buffer
4-8 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
4.4 TCM and cache access priorities
The priorities that apply to the ARM926EJ-S processor for instruction accesses are
shown in Table 4-5. The ARM926EJ-S processor gives highest priority to an address
that is in the instruction TCM region.
The priorities that apply to the ARM926EJ-S processor for data accesses are shown in
Table 4-6. The Harvard arrangement for the TCM and caches requires that data reads
and writes can access the Instruction TCM for both reads and writes. (The column order
for Table 4-6 is deliberately the same as for instruction accesses in Table 4-5.)
Table 4-5 Instruction access priorities to the TCM and cache
Address in
ITCM region
Address in
DTCM region
Cachable in
page descriptor
ARM926EJ-S
behavior
Yes Yes Don't care Access ITCM
Yes No Cachable Access ITCM
Yes No Noncachable Access ITCM
No Don't care Cachable Access ICache
No Don't care Noncachable Access external memory
Table 4-6 Data access priorities to the TCM and cache
Address in
ITCM Region
Address in
DTCM region
Cachable in
page descriptor
ARM926EJ-S
behavior
Yes Yes Don't care Access DTCM
No Yes Cachable Access DTCM
No Yes Noncachable Access DTCM
Yes No Cachable Access ITCM
Yes No Noncachable Access ITCM
No No Cachable Access DCache
No No Noncachable Access external memory

ARM ARM926EJ-S Specifications

General

Brand	ARM
Model	ARM926EJ-S
Category	Computer Hardware
Language	English