Memory Management Unit
3-8 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
3.2.2 First-level fetch
Bits [31:14] of the TTBR are concatenated with bits [31:20] of the MVA to produce a
30-bit address as shown in Figure 3-3.
Figure 3-3 Accessing translation table first-level descriptors
This address selects a 4-byte translation table entry. This is a first-level descriptor for
either a section or a page table.
3.2.3 First-level descriptor
The first-level descriptor returned is a section descriptor, a coarse page table descriptor,
or a fine page table descriptor, or is invalid. Figure 3-4 on page 3-9 shows the format of
a first-level descriptor.
Table index
31 20 19 0
Translation base
31 14 13 0
Translation base
31 14 13 2 1 0
Table index 0 0
First-level descriptor
31 0
Modified virtual address
Translation table base
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