Tightly-Coupled Memory Interface
5-26 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Figure 5-17 Cycle timing of circuit that uses wait states for non sequential accesses
5.5.5 DMA interface example
Figure 5-18 on page 5-27 shows an example TCM subsystem using the DMA interface.
The signal driving DRDMAEN is connected to both the DRDMAEN and DRDMACS
inputs. It is also used to control the multiplexing of the non timing critical signals
(WBL, nRW, and WD), although this is not shown for clarity.
CLK
IRCS
IRWAIT
IRRD
T1 T2 T3 T4 T5 T6
IRADDR
A A+1
I(A)
IRSEQ
T7
A+2
I(A+1)
A+3 A+4
CS
A A A+1 A+2 A+3 A+4
I(A) I(A+2)
I(A+3)
I(A+2)
RD I(A+1)
I(A+3)
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