Instruction Memory Barrier
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 9-5
9.3 Example IMB sequences
The following sequence corresponds to steps 1-4 in IMB operation on page 9-3:
clean_loop
MRC p15, 0, r15, c7, c10, 3 ; clean entire dcache using test and clean
BNE clean_loop
MCR p15, 0, r0, c7, c10, 4 ; drain write buffer
STR rx,[ry] ; nonbuffered store to signal L2 world to
; synchronize
MCR p15, 0, r0, c7, c5, 0 ; invalidate icache
The following sequence illustrates an IMB sequence used after modifying a single
instruction (for example, setting a software breakpoint), with no external
synchronization required:
STR rx,[ry] ; store that modifies instruction at address ry
MCR p15, 0, ry, c7, c10, 1 ; clean dcache single entry (MVA)
MCR p15, 0, r0, c7, c10, 4 ; drain write buffer
MCR p15, 0, ry, c7, c5, 1 ; invalidate icache single entry (MVA)
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