Signal Descriptions
A-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
A.6 Miscellaneous signals
Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor.
Table A-5 Miscellaneous signals
Name Direction Description
BIGENDINIT Input Determines the setting of the B bit in CP15 c1 after a
system reset. When HIGH the reset state of the B bit is 1
(big-endian). When LOW the reset state of the B bit is 0
(little-endian).
CLK Input This clock times all operations of the ARM926EJ-S
design. All outputs change from the rising edge and all
inputs are sampled on the rising edge. The clock can be
stretched in either phase. Through the use of the
DHCLKEN and IHCLKEN signals, this clock also times
AHB operations. Through the use of the DBGTCKEN
signal, this clock also controls JTAG and debug operations.
CFGBIGEND
ARM9EJ-S core
endianness
configuration
Output This signal reflects the setting of the B bit in CP15 c1.
When HIGH, the processor treats bytes in memory as
being in big-endian format. When LOW, memory is treated
as little-endian.
EXTEST Input EXTEST mode test signal. This signal must be LOW
during normal operation.
INTEST Input INTEST mode test signal. This signal must be LOW
during normal operation.
nFIQ
Not fast interrupt
request
Input This is the fast interrupt request signal. This signal must be
synchronous to CLK.
nIRQ
Not interrupt
request
Input This is the interrupt request signal. This signal must be
synchronous to CLK.
SCANENABLE Input Scan enable test signal. This signal must be LOW during
normal operation.
STANDBYWFI Output When HIGH indicates that the ARM926EJ-S processor is
in wait for interrupt mode.
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