Signal Descriptions
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-11
TAPID [31:0] Input This is the ARM926EJ-S device identification (ID) code
test data register, accessible from the scan chains. It must
be tied to 0x07926F0F for an ARM926EJ-S processor
when the device is instantiated.
TESTMODE Input Test mode test signal. This signal must be LOW during
normal operation.
VINITHI
Exception vector
location at reset
Input Determines the reset location of the exception vectors.
When LOW, the vectors are located at
0x00000000
. When
HIGH, the vectors are located at
0xFFFF0000
.
Table A-5 Miscellaneous signals (continued)
Name Direction Description
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