Signal Descriptions
A-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
A.8 TCM interface signals
Table A-7 describes the ARM926EJ-S TCM interface signals.
Table A-7 TCM interface signals
Signal Direction Function
DRADDR[17:0] Output Data TCM address. This is the word address for the
access. Valid during request cycles.
DRCS Output Chip select. Indicates if an access will take place in
the following cycle. Not valid during wait cycles.
DRDMAADDR[17:0] Input Direct memory access address for DTCM memory. If
DRDMAEN is set to 1, then the value of
DRDMAADDR is routed directly through to
DRADDR.
DRDMAEN Input DMA access cycle.
If asserted, DRADDR is directly sourced from
DRDMAADDR, and DRCS is the result of logically
ORing DRDMACS with the chip select value for the
current TCM access.
DRDMACS Input Direct memory access chip-select for DTCM.
DRIDLE Output Data TCM interface idle:
0 = TCM access
1 = no access will take place in the current cycle or
TCM disabled.
Not valid for DMA accesses.
DRnRW Output Data TCM read not write:
0 = read
1 = write.
Indicates if the access is a read or write. Valid during
request cycles.
DRRD[31:0] Input Data TCM read data.
Valid during non-waited data cycles.
DRSEQ Output Request sequential.
Valid during request cycles, asserted during wait
cycles.
Indicates that the address in the current cycle is
sequential to the address used during the previous
request cycle.
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