Caches and Write Buffer
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 4-5
4.3 Enabling the caches
On reset, the ICache and DCache entries are all invalidated and the caches are disabled.
The caches are not accessed for reads or writes. The caches are enabled using the I, C,
and M bits from CP15 c1, and can be enabled independently of one another. Table 4-1
gives the I and M bit settings for the ICache, and the associated behavior. The priority
of the TCM and cache behavior is described in TCM and cache access priorities on
page 4-8.
Table 4-2 gives the page table C bit settings for the ICache (CP15 c1 I bit = M bit = 1).
Table 4-1 CP15 c1 I and M bit settings for the ICache
CP15
c1 I bit
CP15
c1 M bit
ARM926EJ-S behavior
0 - ICache disabled. All instruction fetches are fetched from external
memory (AHB).
1 0 ICache enabled, MMU disabled. All instruction fetches are
cachable, with no protection checks. All addresses are flat mapped,
that is VA = MVA= PA.
1 1 ICache enabled, MMU enabled. Instruction fetches are cachable or
noncachable depending on the page descriptor C bit (see Table 4-2),
and protection checks are performed. All addresses are remapped
from VA to PA, depending on the page entry, that is the VA is
translated to an MVA, and the MVA is remapped to a PA.
Table 4-2 Page table C bit settings for the ICache
Page
table
C bit
Description ARM926EJ-S behavior
0 Noncachable ICache disabled. All instruction fetches are fetched from external
memory.
1 Cachable Cache hit Read from the ICache.
Cache miss Linefill from external memory.
To Next Page
Loading...
Need help?
General
