ARM ARM926EJ-S User Manual

Signal Descriptions
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-3
A.2 AHB related signals
Table A-1 describes the ARM926EJ-S processor AHB related signals.
Table A-1 AHB related signals
Signal name Direction Description
DHADDR[31:0] Output AHB address (data).
DHBL[3:0] Output Byte lane indicator for current transfer.
DHBURST[2:0] Output AHB burst size (data).
DHBUSREQ Output AHB bus request (data).
DHCLKEN Input Signifies the rising edge of HCLK for the data AHB. If
CLK and HCLK are the same frequency, DHCLKEN
must be tied HIGH.
DHGRANT Input AHB bus grant signal (data).
DHLOCK Output AHB bus lock signal (data).
DHPROT[3:0] Output AHB bus access information (data).
DHRDATA[31:0] Input AHB read data (data).
DHREADY Input AHB transfer complete signal (data).
DHRESP[1:0] Input AHB transfer response (data).
DHSIZE[2:0] Output AHB transfer size (data), indicating byte, halfword, or
word. DHSIZE[2] is tied LOW.
DHTRANS[1:0] Output AHB transfer type (data).
DHWDATA[31:0] Output AHB write data (data).
DHWRITE Output AHB transfer direction (data).
HRESETn Input AHB reset signal.
IHADDR[31:0] Output AHB address (instruction).
IHBURST[2:0] Output AHB burst size. (instruction).
IHBUSREQ Output AHB bus request (instruction).
IHCLKEN Input Signifies the rising edge of HCLK for the data AHB. If
CLK and HCLK are the same frequency, IHCLKEN
must be tied HIGH.

ARM ARM926EJ-S Specifications

General

Brand	ARM
Model	ARM926EJ-S
Category	Computer Hardware
Language	English