Debug Support
11-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
The mapping of the register address field to the CP15 registers is shown in Table 11-2.
Writes to either the cache operations register (CRn = c7) or the TLB operations register
(CRn = c8), which require a form of address to select an entry to be manipulated, use
the data value part of the scan chain to provide the address information. The format of
the address field is identical to that used for the value of Rd, for the equivalent MCR
instruction.
Memory system debug operations (CRn = c15), which require an address to be used to
select an entry, use the value held in the debug address register (see Debug and Test
Address Register on page B-4). The format of the address field is identical to that used
for the value of Rd, for the equivalent MCR instruction.
If an invalid instruction is scanned into scan chain 15, it is translated into a read of the
ID register. This means that you can check the output data for ID register reads to
indicate that an invalid instruction has been scanned in.
Table 11-2 Scan chain 15 mapping to CP15 registers
MRC/MCR
instruction field
Scan chain 15
mapping
Opcode_1 [46:44]
Opcode_2 [43:41]
CRn [40:37]
CRm [36:33]
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