Coprocessor Interface
8-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
8.6 Busy-waiting and interrupts
The coprocessor is permitted to stall (busy-wait) the processor during the execution of
a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT on CHSDE[1:0]. When the instruction concerned enters the Execute stage
of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles
as required to keep the instruction in the busy-wait loop.
For interrupt latency reasons the coprocessor might be interrupted while busy-waiting,
causing the instruction to be abandoned using CPPASS. The coprocessor must monitor
the state of CPPASS during every busy-wait cycle. If it is HIGH the instruction must be
executed. If it is LOW the instruction must be abandoned.
Figure 8-8 shows a busy-waited coprocessor instruction being abandoned due to an
interrupt.
Figure 8-8 Busy waiting and interrupts
In Figure 8-8, CPLATECANCEL is also asserted as a result of the Execute
interruption.
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CHSDE[1:0]
CHSEX[1:0]
Coprocessor pipeline
Execute
(WAIT)
Fetch
CPInstr
WAIT
Ignored
Decode
CPLATECANCEL
Execute
(WAIT)
Execute
(WAIT)
Execute
interrupted
WAITWAITWAIT
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