CP15 Test and Debug Registers
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-17
Figure B-10 shows the flow and precedence of CP15 c15 control bits in resolving the
cachable and bufferable attributes of a memory reference.
Figure B-10 Memory region attribute resolution
MMU
Memory
region
remapping
NCNB
NCB
CNB (write-through)
CB (write-back)
NCNB
NCB
CNB (write-through)
CB (write-back)
Force
NCB store
to be
NCNB
MDDEB bit:
MMU disabled,
DCache enabled
Memory Region Remap Register
Debug Override Register
Page table descriptor
FNCB bit:
Force NCB store
to be NCNB
C and B bits
M, C, and I bits
Control Register
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