Bus Interface Unit
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 6-3
6.2 Supported AHB transfers
The ARM926EJ-S processor supports a subset of AHB transfers. The permitted AHB
transfers are described in:
• Memory map
• Transfer size
• Mapping of level one and level two (AHB) attributes on page 6-5
• Byte and halfword accesses on page 6-6
• AHB system considerations on page 6-6
• AHB clocking on page 6-10.
6.2.1 Memory map
The ARM926EJ-S processor is a cached processor with two AHB interfaces. It is a key
system design issue that the D side must be able to access the same memory as the I
side, with the same memory map. This is required not only to load code, but to enable
access to PC-relative literal pools, and for SWI and emulated instruction handlers to
work.
Note
This is unlike some Harvard arrangements whereby the I-bus can be connected to the
ROM and the D-bus only connected to RAM/peripherals.
6.2.2 Transfer size
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four
words, or bursts of eight words. Any ARM9EJ-S core requests that are not 1, 4, or 8
words in size are split into packets of these sizes. For example, an STM of 12 words is
performed on the AHB as a burst of 8 followed by a burst of 4. If a burst is interrupted
because of either a Split or Retry response, or by removal of HGRANT, then the burst
is completed as single transfers. Consequently the ARM926EJ-S processor only uses a
subset of the possible HBURST and HSIZE encodings.
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