Coprocessor Interface
8-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
8.2 LDC/STC
The cycle timing for this operation is shown in Figure 8-3.
Figure 8-3 LDC/STC cycle timing
In Figure 8-3 four words of data are transferred. The number of words transferred is
determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.
As with all other instructions, the ARM9EJ-S core performs the main decode off the
rising edge of the clock during the Decode stage. From this, the core commits to
executing the instruction and so performs an instruction fetch. The coprocessor
instruction pipeline keeps in step with the ARM9EJ-S core by monitoring nCPMREQ.
nCPMREQ is an active LOW signal that indicates if the ARM9EJ-S pipeline has
advanced. CPINSTR is updated with the fetched instruction in the next cycle. This
means that the instruction currently on CPINSTR must enter the Decode stage of the
coprocessor pipeline, and that the instruction in the Decode stage of the coprocessor
pipeline must enter its Execute stage.
During the Execute stage, the condition codes are combined with the flags to determine
if the instruction executes or not. The output CPPASS is asserted HIGH if the
instruction in the Execute stage of the coprocessor pipeline:
• is a coprocessor instruction
• has passed its condition codes.
Decode
Execute
(GO)
Execute
(GO)
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
Coprocessor
pipeline
Memory
Fetch
LDC
Write
Execute
(LAST)
Execute
(GO)
GO
GO GO LAST Ignored
CPDOUT[31:0]
LDC
CPDIN[31:0]
STC
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