Caches and Write Buffer
4-6 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Table 4-3 gives the CP15 c1 C and M bit settings for DCache, and the associated
behavior.
Table 4-4 gives the page table C and B bit settings for the DCache (CP15 c1 C bit = M
bit = 1), and the associated behavior.
Table 4-3 CP15 c1 C and M bit settings for the DCache
CP15
c1 C bit
CP15
c1 M bit
ARM926EJ-S behavior
0 0 DCache disabled. All data accesses are to the external memory.
1 0 DCache enabled, MMU disabled. The C bit is overriden by the M bit
setting, which means that the DCache is effectively disabled. All
data accesses are noncachable, nonbufferable, with no protection
checks. All addresses are flat mapped, that is VA = MVA = PA.
1 1 DCache enabled, MMU enabled. All data accesses are cachable or
noncachable depending on the page descriptor C bit and B bit (see
Table 4-4), and protection checks are performed. All addresses are
remapped from VA to PA, depending on the MMU page table entry,
that is the VA is translated to an MVA, and the MVA is remapped to
a PA.
Table 4-4 Page table C and B bit settings for the DCache
Page
table
C bit
Page
table
B bit
Description ARM926EJ-S behavior
0 0 Noncachable,
nonbufferable
DCache disabled. Read from external memory. Write as
a nonbuffered store(s) to external memory. DCache is not
updated.
0 1 Noncachable,
bufferable
DCache disabled. Read from external memory. Write as
a buffered store(s) to external memory. DCache is not
updated.
1 0 Write-through DCache enabled:
Read hit Read from DCache
Read miss Linefill
Write hit Write to the DCache, and buffered store
to external memory
Write miss Buffered store to external memory
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