Preface
xvi Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
About this manual
This is the Technical Reference Manual for the ARM926EJ-S processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This document has been written for experienced hardware and software engineers who
have previous experience of ARM products, and who wish to use an ARM926EJ-S
processor in their system design.
Using this manual
This document is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an overview of the ARM926EJ-S processor.
Chapter 2 Programmer’s Model
Read this chapter for details of the programmer’s model and
ARM926EJ-S registers.
Chapter 3 Memory Management Unit
Read this chapter for details of the Memory Management Unit (MMU)
and address translation process and how to use the CP15 register to
enable and disable the MMU.
Chapter 4 Caches and Write Buffer
Read this chapter for a description of the instruction cache, the data
cache, the write buffer, and the physical address tag RAM.
Chapter 5 Tightly-Coupled Memory Interface
Read this chapter for a description of the Tightly-Coupled Memory
(TCM) interface and how to use the CP15 region register to enable and
disable the caches. It includes examples on how various RAM types can
be connected.
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