Caches and Write Buffer
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 4-9
4.5 Cache MVA and Set/Way formats
This section shows how the MVA and Set/Way formats of ARM926EJ-S caches map to
a generic virtually indexed, virtually addressed cache.
Figure 4-1 shows a generic, virtually indexed, virtually addressed cache.
Figure 4-1 Generic virtually indexed virtually addressed cache
The ARM926EJ-S cache format is shown in Figure 4-2 on page 4-10.
m
m
m
=
=
=
Vitual index, virtual tag
Tag Index Word
Hit
Read data
=
TA
G
TA
G
3
2
1
3
4
5
6
7
n
TA
G
2
1
3
4
5
6
7
n
2
1
2
1
3
4
5
6
7
n
TAG
0
0
2
1
3
4
5
6
7
n
0 12 m
Byte
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