Tightly-Coupled Memory Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-9
5.3.1 Zero wait state timing
For zero wait state accesses the timing of the TCM interface corresponds to the timing
of a standard SRAM component, with minimal interfacing logic required. Figure 5-2
shows examples of zero wait state accesses on the ITCM interface corresponding to
instruction fetches. All accesses are reads.
Figure 5-2 Instruction side zero wait state accesses
In cycle T1, a nonsequential request is made to address A.
In cycle T2, a sequential request is made to A+1 and data for the access to A is returned.
In cycle T3, no request is made and data is returned for the access to A+1
In cycle T4, a sequential request is made to A+2.
In cycle T5, a nonsequential request is made to address B and data is returned for the
access to A+2.
In cycle T6, a nonsequential request is made to address C and data is returned for the
access to B
It is important to note that, for the ITCM interface, cycles of a sequential request cycle
do not necessarily occur in consecutive bus cycles. Any number of idle request cycles
can occur between two requests, with the second request being marked as being
sequential. The DTCM interface only produces sequential requests during consecutive
bus cycles.
Figure 5-3 on page 5-10 shows examples of data side zero wait state accesses.
CLK
IRCS
IRSEQ
IRADDR A A+1 A+2 B C
IRRD I(A) I(A+1) I(A+2) I(B) I(C)
T1 T2 T3 T4 T5 T6 T7
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