Tightly-Coupled Memory Interface
5-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
5.2 TCM interface signals
The TCM interface is designed to be compatible the timings of standard ASIC SRAM
components, allowing connection to single cycle SRAM with minimal interfacing logic
required. For standard SRAM the chip-select, address, and write data/control signals are
setup in one cycle, and the read or write operation takes place in the next cycle.
5.2.1 Data interface signals
The signals in the DTCM interface can be grouped by function into four categories.
• Control signals
— DRCS
— DRWAIT
— DRIDLE
• Address and attribute signals
— DRSEQ
— DRADDR[17:0]
— DRWBL[3:0]
— DRnRW
• Data signals
— DRRD[31:0]
— DRWD[31:0]
• DMA signals
— DRDMAEN
— DRDMACS
— DRDMAADDR[17:0].
Control signals
The control signals for the data interface are:
DRCS
DRCS is used to indicate that an access will commence in the following cycle. For
simple zero wait state TCM systems the DRCS signals corresponds directly to a
memory chip select signal. For more complex systems DRCS corresponds to a memory
request signal.
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