Tightly-Coupled Memory Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-5
DRWAIT
DRWAIT is used to extend a TCM transfer by inserting wait states. The timing of the
DRWAIT signal is a cycle ahead of the cycle in which the data transfer takes place,
which means that if an access is to be waited, DRWAIT must be asserted in the same
cycle as DRCS and deasserted one cycle before the data transfer takes place.
DRIDLE
The DRIDLE signal provides an early indication that no TCM access will take place in
the current cycle.
Address and attribute signals
All of the address and attribute signals are valid when DRCS is asserted (and valid),
with the exception of DRSEQ which also has a defined value during wait states (when
DRCS is not valid).
DRSEQ
When DRCS is asserted and valid, DRSEQ indicates if the address for the current TCM
access is sequential to the previous access. During wait states DRSEQ is forced HIGH.
DRADDR[17:0]
DRADDR is the word (32 bit) address for the transfer.
DRnRW
DRnRW indicates if the access is a read or a write.
DRWBL[3:0]
DRWBL is used to indicate which byte(s) of an address should be updated for write
accesses. This is dependant on the address, the size of the transfer, and the current
endianess setting. DRWBL is b0000 for reads.
Data signals
The data signals are:
DRRD[31:0]
DRRD is the read data returned by the TCM. For zero wait state systems, DRRD is
valid in the cycle after DRCS. For systems with wait states, DRRD is valid in the cycle
after DRWAIT is deasserted.
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