Tightly-Coupled Memory Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-27
Figure 5-18 TCM subsystem that uses the DMA interface
5.5.6 Integrating RAM test logic
The memory used to implement TCM might require some form of test access, typically
by a BIST controller. Generally this is done by adding a collar of multiplexors around
the memory inputs. However, this method will add undesirable delays to the chip select
and address signals. This can be avoided by using the DMA interface to perform the
multiplexing of address and chip-select values. This is shown in Figure 5-19 on
page 5-28.
SRAM
DRWD[31:0]
DMARD[31:0]
DRWBL[3:0]
DRDMAADDR[17:0]
CS
WD[31:0]
ARM926EJ-S
1
0
DMA
1
0
1
0
DMAWBL[3:0]
DMAnRW
DMAWD[31:0]
DRDMAEN
DMAADDR[31:0]
DRDMAEN
DRDMACS
DRnRW
RD[31:0]
WBL[3:0]
nRW
A[17:0]DRADDR[17:0]
DRCS
DRWAIT
DRSEQ
DRRD[31:0]
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