Tightly-Coupled Memory Interface
5-8 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
5.3 TCM interface bus cycle types and timing
The TCM bus interface is pipelined to enable back-to-back accesses to TCM memory
with zero wait states. For each TCM access there is one request cycle and one or more
data cycles. Figure 5-1 shows a multi-cycle data side TCM access.
Figure 5-1 Multi-cycle data side TCM access
The first cycle is a request cycle (request A), where all of the TCM interface output
signals are valid. The TCM subsystem responds on DRWAIT, indicating that the access
will not complete in the following cycle. The cycle following the request cycle (data
A-1) is the first waited data cycle. In this cycle the values of DRADDR, DRnRW, and
DRWBL are no longer valid and their value is non-deterministic, and DRSEQ is
asserted. The value on DRWD remains the same if the access is a write. As in the
request cycle DRWAIT indicates if the access will complete in the following cycle. In
the penultimate data cycle (data A-n-1) DRWAIT is deasserted indicating that the
access will complete in the next cycle. For write accesses, this cycle is the last cycle
where DRWD remains valid. If the last data cycle of the access (data A-n) is a read then
DRRD contains valid read data. Because of the pipelined nature of the interface, the last
data cycle of one access can overlap a request cycle of the next access.
data A-1
data A -n
data A-(n-1)
request A
request B
DRADDR[17:0]
DRnRW
DRWBL[3:0]
DRWD[31:0]
DRSEQ
DRWAIT
DRRD[31:0]
Data valid
CLK
DRCS
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