Bus Interface Unit
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 6-9
Figure 6-2 Multi-AHB system example
If both AHB systems operate at the same frequency, DHCLKEN and IHCLKEN must
be tied together. See AHB clocking on page 6-10 for more details.
The AHB clock for each system, HCLK1 and HCLK2, must be synchronized to the
ARM926EJ-S clock signal CLK.
Memory coherency
Because of the Harvard nature of the ARM926EJ-S processor, instruction and data flow
order cannot be guaranteed, and the arbitration order of the two masters can be
considered to be arbitrary.
For single and multi-layer AHB systems:
• the arbitration priority of the two masters determines which of the masters is
granted the bus, if both make a simultaneous request
• if the granted master receives a Split or Retry response, the other master can be
granted the bus and complete its transaction before the split master completes.
For multi-AHB systems:
• the two systems can be operating at different frequencies
• the memory slaves can insert waits and/or issue Split or Retry responses.
If the sequence of flow is critical, in self-modifying code for example, an Instruction
Memory Barrier (IMB) must be used to force coherency. See Chapter 9 Instruction
Memory Barrier for more details.
DHCLKEN
D-AHB
IHCLKEN
I-AHB
D-AHB
subsystem
I-AHB
subsystem
D-AHB to I-AHB bridge
ARM926EJ-S
processor
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