Caches and Write Buffer
4-2 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
4.1 About the caches and write buffer
The ARM926EJ-S processor includes:
• an Instruction Cache (ICache)
• a Data Cache (DCache)
• a write buffer.
The size of the caches can be from 4KB to 128KB, in power of two increments.
The caches have the following features:
• The caches are virtual index, virtual tag, addressed using the Modified Virtual
Address (MVA). This enables the avoidance of cache cleaning and/or invalidating
on context switch.
• The caches are four-way set associative, with a cache line length of eight words
per line (32 bytes per line), and with two dirty bits in the DCache.
• The DCache supports write-through and write-back (or copyback) cache
operations, selected by memory region using the C and B bits in the MMU
translation tables.
• Allocate on read-miss is supported. The caches perform critical-word first cache
refilling.
• Pseudo-random or round-robin replacement, selectable by the RR bit in CP15 c1.
• Cache lockdown registers enable control over which cache ways are used for
allocation on a linefill, providing a mechanism for both lockdown and controlling
cache pollution.
• The DCache stores the Physical Address (PA) tag corresponding to each DCache
entry in the tag RAM for use during cache line write-backs, in addition to the
Virtual Address tag stored in the tag RAM. This means that the MMU is not
involved in DCache write-back operations, removing the possibility of TLB
misses related to the write-back address.
• The PLD data preload instruction does not cause data cache linefills. It is treated
as a NOP instruction.
• Cache maintenance operations to provide efficient invalidation of:
— the entire DCache or ICache
— regions of the DCache or ICache
— regions of virtual memory.
They also provide operations for efficient cleaning and invalidation of:
— the entire DCache
— regions of the DCache
— regions of virtual memory.
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