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ARM ARM926EJ-S User Manual
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ARM DDI0198D
Copyright ©
2001-2003
ARM Limited. A
ll rights reserved.
4-1
Chapt
er
4
Cac
hes
and Write Buff
er
This chapter descr
ibes the
Inst
ructi
on Cac
he
(ICache),
the
Data Cache
(DCache), an
d
the write bu
f
fer
. It contains the follo
wing sections:
•
About the cac
hes and
write b
uf
fer
on page
4-2
•
Write buf
fer
on pag
e
4-4
•
Enabling the caches
on page
4-5
•
TCM and cac
he access priorities
on page
4-8
•
Cac
he MV
A and Set/W
ay formats
on p
age
4-
9.
96
98
Table of Contents
Default Chapter
2
Change History
2
Copyright © 2001-2003 Arm Limited. All Rights Reserved
2
Table of Contents
3
List of Tables
7
Preface
16
About this Manual
16
Key to Timing Diagram Conventions
19
Feedback
21
Chapter 1 Introduction
23
About the ARM926EJ-S Processor
24
Figure 1-1 ARM926EJ-S Block Diagram
25
Figure 1-2 ARM926EJ-S Interface Diagram (Part One)
26
Figure 1-3 ARM926EJ-S Interface Diagram (Part Two)
27
Chapter 2 Programmer's Model
29
About the Programmer's Model
30
Summary of ARM926EJ-S System Control Coprocessor (CP15) Registers
31
Table 2-1 CP15 Register Summary
31
Table 2-2 Address Types in ARM926EJ-S
32
Table 2-3 CP15 Abbreviations
33
Figure 2-1 CP15 MRC and MCR Bit Pattern
33
Register Descriptions
35
Table 2-4 Reading from Register C0
35
Table 2-5 Register 0, ID Code
36
Table 2-6 Ctype Encoding
37
Figure 2-2 Cache Type Register Format
37
Figure 2-3 Dsize and Isize Field Format
37
Table 2-7 Cache Size Encoding (M=0)
38
Table 2-8 Cache Associativity Encoding (M=0)
38
Table 2-9 Line Length Encoding
39
Table 2-10 Example Cache Type Register Format
39
Figure 2-4 TCM Status Register Format
40
Table 2-11 Control Bit Functions Register C1
41
Figure 2-5 Control Register Format
41
Table 2-12 Effects of Control Register on Caches
43
Table 2-13 Effects of Control Register on TCM Interface
44
Figure 2-6 TTBR Format
45
Table 2-14 Domain Access Control Defines
46
Figure 2-7 Register C3 Format
46
Table 2-15 FSR Bit Field Descriptions
47
Figure 2-8 FSR Format
47
Table 2-16 FSR Status Field Encoding
48
Table 2-17 Function Descriptions Register C7
49
Table 2-18 Cache Operations C7
50
Figure 2-9 Register C7 MVA Format
51
Figure 2-10 Register C7 Set/Way Format
52
Table 2-19 Register C8 TLB Operations
53
Figure 2-11 Register C8 MVA Format
54
Table 2-20 Cache Lockdown Register Instructions
55
Figure 2-12 Cache Lockdown Register C9 Format
55
Table 2-21 Cache Lockdown Register L Bits
56
Table 2-22 TCM Region Register Instructions
57
Table 2-23 TCM Region Register C9
58
Table 2-24 TCM Size Field Encoding
58
Figure 2-13 TCM Region Register C9 Format
58
Table 2-25 Programming the TLB Lockdown Register
60
Figure 2-14 TLB Lockdown Register Format
60
Table 2-26 FCSE PID Register Operations
62
Figure 2-15 Process ID Register Format
62
Table 2-27 Context ID Register Operations
63
Figure 2-16 Context ID Register Format
63
Chapter 3 Memory Management Unit
66
About the MMU
66
Table 3-1 MMU Program-Accessible CP15 Registers
68
Address Translation
69
Figure 3-5 Section Descriptor
69
Figure 3-1 Translation Table Base Register
70
Figure 3-2 Translating Page Tables
71
Figure 3-3 Accessing Translation Table First-Level Descriptors
72
Table 3-2 First-Level Descriptor Bits
73
Figure 3-4 First-Level Descriptor
73
Table 3-3 Interpreting First-Level Descriptor Bits [1:0]
74
Table 3-4 Section Descriptor Bits
75
Figure 3-6 Coarse Page Table Descriptor
75
Table 3-5 Coarse Page Table Descriptor Bits
76
Figure 3-7 Fine Page Table Descriptor
76
Table 3-6 Fine Page Table Descriptor Bits
77
Figure 3-8 Section Translation
78
Table 3-7 Second-Level Descriptor Bits
79
Figure 3-9 Second-Level Descriptor
79
Table 3-8 Interpreting Page Table Entry Bits [1:0]
80
Figure 3-11 Small Page Translation from a Coarse Page Table
82
Figure 3-12 Tiny Page Translation from a Fine Page Table
83
MMU Faults and CPU Aborts
85
Table 3-9 Priority Encoding of Fault Status
86
Table 3-10 FAR Values for Multi-Word Transfers
87
Domain Access Control
88
Table 3-11 Domain Access Control Register, Access Control Bits
88
Table 3-12 Interpreting Access Permission (AP) Bits
88
Fault Checking Sequence
90
Figure 3-13 Sequence for Checking Faults
90
External Aborts
93
TLB Structure
95
Chapter 4 Caches and Write Buffer
98
About the Caches and Write Buffer
98
Write Buffer
100
Enabling the Caches
101
Table 4-1 CP15 C1 I and M Bit Settings for the Icache
101
Table 4-2 Page Table C Bit Settings for the Icache
101
Table 4-3 CP15 C1 C and M Bit Settings for the Dcache
102
Table 4-4 Page Table C and B Bit Settings for the Dcache
102
TCM and Cache Access Priorities
104
Table 4-5 Instruction Access Priorities to the TCM and Cache
104
Table 4-6 Data Access Priorities to the TCM and Cache
104
Cache MVA and Set/Way Formats
105
Figure 4-1 Generic Virtually Indexed Virtually Addressed Cache
105
Table 4-7 Values of S and NSETS
106
Figure 4-2 ARM926EJ-S Cache Associativity
106
Figure 4-3 ARM926EJ-S Cache Set/Way/Word Format
107
Chapter 5 Tightly-Coupled Memory Interface
110
About the Tightly-Coupled Memory Interface
110
TCM Interface Signals
112
Table 5-1 Relationship between DMDMAEN, DRDMACS, and DRIDLE
114
TCM Interface Bus Cycle Types and Timing
116
Figure 5-1 Multi-Cycle Data Side TCM Access
116
Figure 5-2 Instruction Side Zero Wait State Accesses
117
Figure 5-3 Data Side Zero Wait State Accesses
118
Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS
119
Figure 5-5 DMA Access Interaction with Normal DTCM Accesses
120
Figure 5-6 Generating a Single Wait State for ITCM Accesses Using IRWAIT
121
Figure 5-7 State Machine for Generating a Single Wait State
122
Figure 5-8 Loopback of SEQ to Produce a Single Cycle Wait State
122
Figure 5-9 Cycle Timing of Loopback Circuit
123
Figure 5-10 DMA with Single Wait State for Nonsequential Accesses
124
Figure 5-11 Cycle Timing of Circuit with DMA and Single Wait State for Nonsequential Accesses
125
TCM Programmer's Model
127
TCM Interface Examples
128
Figure 5-12 Zero Wait State RAM Example
128
Figure 5-13 Byte-Banks of RAM Example
129
Figure 5-14 Optimizing for Power
131
Figure 5-15 Optimizing for Speed
132
Figure 5-16 TCM Subsystem that Uses Wait States for Nonsequential Accesses
133
Figure 5-17 Cycle Timing of Circuit that Uses Wait States for Non Sequential Accesses
134
Figure 5-18 TCM Subsystem that Uses the DMA Interface
135
Figure 5-19 TCM Test Access Using bist
136
TCM Access Penalties
137
TCM Write Buffer
138
Using Synchronous SRAM as TCM Memory
139
TCM Clock Gating
140
Chapter 6 Bus Interface Unit
141
About the Bus Interface Unit
142
Supported AHB Transfers
143
Table 6-1 Supported HBURST Encodings
144
Table 6-2 IHPROT[3:0] and DHPROT[3:0] Attributes
145
Figure 6-1 Multi-Layer AHB System Example
148
Figure 6-2 Multi-AHB System Example
149
Figure 6-3 AHB Clock Relationships
150
Chapter 7 Noncachable Instruction Fetches
153
About Noncachable Instruction Fetches
154
Figure 8-7 Privileged Instructions
157
Chapter 8 Coprocessor Interface
158
About the ARM926EJ-S External Coprocessor Interface
158
Figure 8-1 Producing a Coprocessor Clock
158
Figure 8-2 Coprocessor Clocking
158
Ldc/Stc
160
Figure 8-3 LDC/STC Cycle Timing
160
Table 8-1 Handshake Signal Encoding
161
Mcr/Mrc
162
Figure 8-4 MCR/MRC Cycle Timing
162
Figure 8-5 Interlocked MCR
163
Cdp
164
Figure 8-6 Latecanceled CDP
164
Privileged Instructions
165
Busy-Waiting and Interrupts
166
Figure 8-8 Busy Waiting and Interrupts
166
Cpburst
167
Table 8-2 CPBURST Encoding
167
Cpabort
168
Figure 8-9 CPBURST and CPABORT Timing
168
Ncpinstrvalid
169
Connecting Multiple External Coprocessors
170
Figure 8-10 Arrangement for Connecting Two Coprocessors
170
Chapter 9 Instruction Memory Barrier
171
About the Instruction Memory Barrier Operation
172
IMB Operation
173
Example IMB Sequences
175
Chapter 10 Embedded Trace Macrocell Support
177
About Embedded Trace Macrocell Support
178
Chapter 11 Debug Support
181
About Debug Support
182
Table 11-1 Scan Chain 15 Format
182
Table 11-2 Scan Chain 15 Mapping to CP15 Registers
184
Chapter 12 Power Management
185
About Power Management
186
Figure 12-1 Deassertion of STANDBYWFI after an IRQ Interrupt
186
Figure 12-2 Logic for Stopping ARM926EJ-S Clock During Wait for Interrupt
187
Appendix A Signal Descriptions
189
Table A-4 JTAG Signals
189
Table A-5 Miscellaneous Signals
189
Signal Properties and Requirements
190
AHB Related Signals
191
Table A-1 AHB Related Signals
191
Coprocessor Interface Signals
193
Table A-2 Coprocessor Interface Signals
193
Debug Signals
195
Table A-3 Debug Signals
195
JTAG Signals
197
Miscellaneous Signals
198
ETM Interface Signals
200
Table A-6 ETM Interface Signals
200
TCM Interface Signals
202
Table A-7 TCM Interface Signals
202
CP15 Test and Debug Registers
207
Appendix B CP15 Test and Debug Registers
208
About the Test and Debug Registers
208
Figure B-1 CP15 MRC and MCR Bit Pattern
208
Figure B-2 Rd Format for Selecting Main TLB Entry
212
Figure B-3 Rd Format for Accessing MVA Tag of Main or Lockdown TLB Entry
213
Table B-5 Encoding of the TLB MVA Tag Bit Fields
213
Figure B-4 Rd Format for Accessing PA and AP Data of Main or Lockdown TLB Entry
214
Table B-6 Encoding of the TLB Entry PA and AP Bit Fields
214
Table B-7 Main TLB Mapping to Mmuxwd
215
Figure B-5 Write to the Data RAM
216
Figure B-6 Rd Format for Selecting Lockdown TLB Entry
217
Table B-8 Encoding of the Lockdown TLB Entry-Select Bit Fields
217
Figure B-7 Cache Debug Control Register Format
218
Table B-9 Cache Debug Control Register Bit Assignments
218
Figure B-8 MMU Debug Control Register Format
220
Table B-10 MMU Debug Control Register Bit Assignments
220
Figure B-9 Memory Region Remap Register Format
221
Table B-11 Memory Region Remap Register Instructions
221
Table B-12 Encoding of the Memory Region Remap Register
222
Table B-13 Encoding of the Remap Fields
222
Table B-1 Debug Override Register
209
Table B-2 Trace Control Register Bit Assignments
211
Table B-3 MMU Test Operation Instructions
211
Table B-4 Encoding of the Main TLB Entry-Select Bit Fields
212
Figure B-10 Memory Region Attribute Resolution
223
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ARM ARM926EJ-S Specifications
General
Brand
ARM
Model
ARM926EJ-S
Category
Computer Hardware
Language
English
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