Tightly-Coupled Memory Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-29
5.6 TCM access penalties
The data side of the ARM926EJ-S core can access the ITCM. To maximize the
performance of the ITCM, data read accesses to the ITCM are pipelined. The
ARM926EJ-S core is stalled for two cycles to enable the pipeline read to complete. This
is the only ARM926EJ-S TCM interface stall scenario. The inclusion of a write buffer
in the TCM controller has eliminated all other sources of potential stalling for zero wait
state TCM.
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