CP15 Test and Debug Registers
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-3
The reset state of the Debug Override Register is
0x0
.
Bit 13, MMU disabled, DCache enabled behavior
This bit changes the behavior when the MMU is disabled but the DCache
is enabled. During normal operation, if the MMU is disabled, all data
accesses are treated as being NCNB. If Bit 13 is set with the MMU
disabled, and the DCache is enabled, all data accesses are treated as WT.
Note
This behavior can be overridden using the memory region register.
Bit 14, disable NCB stores (force NCNB)
You can use this bit to force all NCB stores to be treated as NCNB stores
at level one. This bit overrides the settings in both the MMU page tables
and the memory region remap register.
Table B-1 Debug Override Register
Bits Function or name Description
[31:20] Reserved Read = Unpredictable
Write = Should Be Zero
[19] Test and clean all 0 = Default behavior for test and clean instructions
1 = Modifies the behavior of test and clean, and test, clean, and
invalidate instructions so that they act on the complete cache
[18] Abort data TLB miss 0 = Do not abort DTLB miss
1 = Abort DTLB miss
[17] Abort instruction TLB miss 0 = Do not abort ITLB miss
1 = Abort ITLB miss
[16] Disable NC instruction prefetching 0 = Enable prefetching
1 = Disable prefetching
[15] Disable block-level clock gating 0 = Enable block-level clock gating
1 = Disable block-level clock gating
[14] Disable NCB stores (force NCNB) 0 = Enable NCB stores
1 = Disable NCB stores (force NCNB)
[13] MMU disabled, DCache enabled
behavior
0 = If MMU disabled. level one access NCNB
1 = If MMU disabled and DCache enabled level one access WT
[12:0] Reserved Read = Unpredictable
Write = Should Be Zero
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