ARM ARM926EJ-S - Table of Contents

ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. iii
Contents
ARM926EJ-S Technical Reference Manual
Preface
About this manual ........................................................................................ xvi
Feedback ..................................................................................................... xxi
Chapter 1 Introduction
1.1 About the ARM926EJ-S processor ............................................................. 1-2
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3
2.3 Register descriptions .................................................................................. 2-7
Chapter 3 Memory Management Unit
3.1 About the MMU ........................................................................................... 3-2
3.2 Address translation ..................................................................................... 3-5
3.3 MMU faults and CPU aborts ..................................................................... 3-21
3.4 Domain access control .............................................................................. 3-24
3.5 Fault checking sequence .......................................................................... 3-26
3.6 External aborts .......................................................................................... 3-29
3.7 TLB structure ............................................................................................ 3-31