Contents
iv Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Chapter 4 Caches and Write Buffer
4.1 About the caches and write buffer .............................................................. 4-2
4.2 Write buffer ................................................................................................. 4-4
4.3 Enabling the caches ................................................................................... 4-5
4.4 TCM and cache access priorities ............................................................... 4-8
4.5 Cache MVA and Set/Way formats .............................................................. 4-9
Chapter 5 Tightly-Coupled Memory Interface
5.1 About the tightly-coupled memory interface ............................................... 5-2
5.2 TCM interface signals ................................................................................. 5-4
5.3 TCM interface bus cycle types and timing .................................................. 5-8
5.4 TCM programmer’s model ........................................................................ 5-19
5.5 TCM interface examples ........................................................................... 5-20
5.6 TCM access penalties .............................................................................. 5-29
5.7 TCM write buffer ....................................................................................... 5-30
5.8 Using synchronous SRAM as TCM memory ............................................ 5-31
5.9 TCM clock gating ...................................................................................... 5-32
Chapter 6 Bus Interface Unit
6.1 About the bus interface unit ........................................................................ 6-2
6.2 Supported AHB transfers ............................................................................ 6-3
Chapter 7 Noncachable Instruction Fetches
7.1 About noncachable instruction fetches ....................................................... 7-2
Chapter 8 Coprocessor Interface
8.1 About the ARM926EJ-S external coprocessor interface ............................ 8-2
8.2 LDC/STC .................................................................................................... 8-4
8.3 MCR/MRC .................................................................................................. 8-6
8.4 CDP ............................................................................................................ 8-8
8.5 Privileged instructions ................................................................................. 8-9
8.6 Busy-waiting and interrupts ...................................................................... 8-10
8.7 CPBURST ................................................................................................ 8-11
8.8 CPABORT ................................................................................................ 8-12
8.9 nCPINSTRVALID ..................................................................................... 8-13
8.10 Connecting multiple external coprocessors .............................................. 8-14
Chapter 9 Instruction Memory Barrier
9.1 About the instruction memory barrier operation ......................................... 9-2
9.2 IMB operation ............................................................................................. 9-3
9.3 Example IMB sequences ............................................................................ 9-5
Chapter 10 Embedded Trace Macrocell Support
10.1 About Embedded Trace Macrocell support .............................................. 10-2
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