Tightly-Coupled Memory Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-3
memory. The TCM interface contains a two entry write buffer, which avoids the need
for stall cycles because of the mismatch between the ARM9EJ-S native memory
interface, and the requirements for standard SRAM.
TCM accesses can be extended by using the IRWAIT/DRWAIT inputs to generate wait
states. However, the timing of these and other interface signals is such that the types of
memory sub-systems that can be implemented are limited. For example schemes that
require an address decode to determine if a wait-state should be inserted are not possible
if operating at maximum frequency.
DMA access can be performed either by using the IRWAIT/DRWAIT signals to insert
wait states during a DMA access, or by using the dedicated DMA interface, which
avoids the need to externally multiplex critical interface signals when single cycle
access memory is used.
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