Coprocessor Interface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 8-3
This is one technique for generating a clock that reflects the ARM9EJ-S core pipeline
advancing. If CPCLKEN is LOW on the rising edge of CPCLK then the ARM9EJ-S
core pipeline is stalled and the coprocessor pipeline should not advance.
Coprocessor instructions
There are three classes of coprocessor instructions:
LDC or STC Load coprocessor register from memory or store coprocessor
register to memory.
MCR/MCRR or MRC/MRRC
Register transfer between the coprocessor and the ARM processor
core.
CDP Coprocessor data operation.
Examples of how a coprocessor must execute these instruction classes are given in:
• LDC/STC on page 8-4
• MCR/MRC on page 8-6
• CDP on page 8-8.
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