Epson S1D13706 - Table 8-3: PCLK Divide Selection; Table 8-4: PCLK Source Selection

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Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
bits 6-4 PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
bits 1-0 PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
Pixel Clock Configuration Register
REG[05h] Read/Write
n/a PCLK Divide Select Bits 2-0 n/a PCLK Source Select Bits 1-0
76543 210
Table 8-3: PCLK Divide Selection
PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio
000 1:1
001 2:1
010 3:1
011 4:1
1XX 8:1
Table 8-4: PCLK Source Selection
PCLK Source Select Bits PCLK Source
00 MCLK
01 BCLK
10 CLKI
11 CLKI2